1. Field of the Invention
The present invention relates to a semiconductor device and a data processing system including the same, and more particularly relates to a semiconductor device capable of reducing its power consumption in the standby state and a data processing system including the semiconductor device.
2. Description of Related Art
In recent years, an operation voltage of semiconductor devices is steadily reduced for reducing their power consumption. Some of currently available semiconductor devices have an operation voltage as low as 1 V. However, a threshold voltage of a transistor needs to be reduced following the reduction in the operation voltage, and this fact leads to a problem that a subthreshold current of the transistor in a non-conductive state is increased. As a solution to this problem, a power gating control method in which power lines are separated into main power lines and dummy power lines has been proposed in Japanese Patent Application Laid-open Nos. 2000-82950 and H08-227580.
Japanese Patent Application Laid-open Nos. 2000-82950 and H08-227580 disclose a technique in which a power node on a high side is connected to a main power line and a power node on a low side is connected to a dummy power line for a logic circuit that needs to output a high level at the time of standby, and a power node on a high side is connected to a dummy power line and a power node on a low side is connected to a main power line for a logic circuit that needs to output a low level at the time of standby. According to this technique, because a source of a transistor that is turned off in a standby mode is invariably connected to a dummy power line, by reducing an electric potential of a dummy power line on a high side at the time of standby and increasing an electric potential of a dummy power line on a low side, a subthreshold current of the transistor that is turned off can be reduced.
However, in the semiconductor devices disclosed in Japanese Patent Application Laid-open Nos. 2000-82950 and H08-227580, a source potential of a transistor that is turned on in the standby mode is the same as a source potential of the transistor in an active mode. Therefore, a leakage current that flows between agate electrode of the transistor that is turned on in the standby mode and a substrate (a back gate) cannot be reduced. Also, a leakage current that flows between a drain of a transistor that is turned off in the standby mode and a substrate (a back gate) cannot be reduced sufficiently.